1. Field of the Invention
The present invention relates to a semiconductor storage device. For example, the invention relates to a multi-level NAND-type flash memory having a charge accumulation layer and a control gate.
2. Description of the Related Art
Conventionally, a NAND-type flash memory is well known as a nonvolatile semiconductor memory. A self-boost type memory is widely used in the NAND-type flash memory. In the self-boost type memory, a channel potential is raised by coupling with a gate in a write-inhibit cell, and thereby electrons are prevented from being injected into a floating gate.
In the self-boost type memory, it gas been found that boost efficiency is decreased in the use of a memory cell in which data is written to raise a threshold. Therefore, for example, Jpn. Pat. Appln. KOKAI Publication No. 10-283788 proposes a technique in which the boost efficiency is improved using only an erasing cell by cutting off a channel from a selected memory cell to a memory cell on a source line side.
However, in the conventional technique, the channel cannot be cut off by a threshold voltage of the memory cell, and the boost efficiency is decreased, which results in a problem of wrongly writing the data in the write-protect cell.
During a write operation of the memory cell adjacent to a selection transistor on a source side, sometimes electrons are generated by GIDL (Gate Induced Drain Leakage) in an impurity diffusion layer shared by the memory cell and the selection transistor. The generated electrons act as hot electrons, and are accumulated in a floating gate of the memory cell, which results in a problem of generating the wrong write.